DesignCon 2007 UltraSPARC Processor Emulation Verification: Getting HW/SW right the first time

With reduced time-to-market and highly competitive marketplace, it is now important, more than ever, to get the product right the first time! And this is no different for latest generation CoolThreads UltraSPARC T1 processor. The UltraSPARC T1 processor represents one of the highest throughput and most eco-responsible processor featuring unique multi-core, multi-threaded design with up to 32 simultaneous threads, posing new verification challenges. We embraced this verification challenge by enhancing verification efficiency by adapting aggressive changes in methodology, state-of-art tools and technologies. The UltraSPARC T1 design along with system-level test bench is unusually large: 35+ Million Gates. This posed a capacity and performance issue for all verification tools making it difficult for us to run the required number of verification cycles in timely fashion to attain high verification confidence to tape-out the design. This is one of the driving factors that that requires us to pro-actively use a blend of internal and external tools. Our functional verification methodology encompasses best-of-breed simulation, formal and emulation tools. At Sun we have successfully deployed acceleration and emulation technologies to perform system integration and functional verification tasks prior to design tape-out that are traditionally performed after arrival of silicon. Acceleration from multiple vendors is a key ingredient of our block, chip and system level functional verification methodologies. This paper depicts revolutionary usage of emulation technology at Sun in general and in particular the role it played in verification of our latest generation CoolThreads UltraSPARC T1 processor. Emulation stepped in to take on challenges of running long directed, random self-checking and DFT diagnostics just where traditional SW simulators run out of gas. Our system models are so large that SW simulators literally come to a crawl. We will discuss emulation modeling, capacity and performance optimization techniques along with key factors enabling our success. We will also describe methodologies to enable firmware and SW development and testing prior to design tape out. We were able to cut the product development cycle in roughly half. The focus of this presentation is to depict issues related to verification of large SoC and innovative techniques employed to resolve them successfully.